`timescale 1ns / 1ps

////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer:
//
// Create Date:   21:41:08 01/24/2013
// Design Name:   ppalu
// Module Name:   E:/ParaCPU/shaoxia-project/hdl/src/tb_modules/tb_ppalu.v
// Project Name:  ise_ParaCPU
// Target Device:  
// Tool versions:  
// Description: 
//
// Verilog Test Fixture created by ISE for module: ppalu
//
// Dependencies:
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
////////////////////////////////////////////////////////////////////////////////
`include "s:/define.v"
module tb_ppalu;

	// Inputs
	reg clk;
	reg rst_n;
	reg alu_en;
	reg [7:0] E_opcode;
	reg [1:0] E_opcode_supp;
	reg [31:0] E_valB;
	reg [31:0] E_valA;

	// Outputs
	wire [31:0] e_valE;
	wire e_valE_valid;
	wire e_setcc;
	wire [2:0] e_alucc;

	// Instantiate the Unit Under Test (UUT)
	ppalu uut (
		.clk(clk), 
		.rst_n(rst_n), 
		.alu_en(alu_en), 
		.E_opcode(E_opcode), 
		.E_opcode_supp(E_opcode_supp), 
		.E_valB(E_valB), 
		.E_valA(E_valA), 
		.e_valE(e_valE), 
		.e_valE_valid(e_valE_valid), 
		.e_setcc(e_setcc), 
		.e_alucc(e_alucc)
	);

	initial begin
		// Initialize Inputs
		clk = 0;
		rst_n = 0;
		alu_en = 0;
		E_opcode = 0;
		E_opcode_supp = 0;
		E_valB = 0;
		E_valA = 0;

		// Wait 100 ns for global reset to finish
		#100 rst_n=1;
        
		// Add stimulus here
		ExecIns({`PP_INS,`ADD},32'd99,32'd77);
		ExecIns({`PP_INS,`SUB},32'd99,32'd77);
		ExecIns({`PP_INS,`MULT},32'd99,32'd77);
	end
	
	always #2 clk=~clk;
	
	task ExecIns;
	input [7:0] OP;
	input [31:0] A;
	input [31:0] B;
	begin
		@ (posedge clk)
			#0.1;
		alu_en<=1;
		E_opcode<=OP;
		E_valA<=A;
		E_valB<=B;
		
		while(!e_valE_valid)
		begin
			@ (posedge clk)
			#0.1;
		end
		alu_en<=0;	
		@ (posedge clk)
			#0.1;
	end
	endtask
      
endmodule

